PT Journal AU Simmich, S Bahr, A Rieger, R TI Noise Efficient Integrated Amplifier Designs for Biomedical Applications SO Electronics PY 2021 PU MDPI AG DI 10.3390/electronics10131522 WP https://macau.uni-kiel.de/receive/macau_mods_00001554 LA en DE noise efficiency; NEF; lateral BJT; chopper stabilized; OTA; inverter based; current reuse; folded-cascode; multistage; low noise; low power; CMOS SN 2079-9292 AB The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√Hz with a 10 µA bias current, which results in a NEF of 1.2. PI Basel ER