Timing Analysis for the Precision Timed ARM Processor

Most modern processors leverage technologies that improve average-case performance but render worst case execution time (WCET) analysis difficult, often leading to imprecise values. These include complex cache concepts and intricate pipeline structures. In contrast, precision-timed (PRET) architectures are designed to provide predictable timing and precise timing control. Interleaved pipelines and scratchpad memories are main enablers of this concept. The instruction sets of according processor implementations are provided with additional instructions that give the possibility of timing control to the programmer. The Precision Timed ARM (PTARM) processor is an ARM based realization of a PRET architecture. This work is focussed on adapting an existing WCET analysis tool, OTAWA, for the PTARM processor. The analysis of arbitrary parts of C-Code is enabled as well as the automatic matching of different code segments and the calculation of maximal cycle time amounts for different combinations.

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